--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 13.4
--  \   \         Application : sch2hdl
--  /   /         Filename : top.vhf
-- /___/   /\     Timestamp : 11/23/2017 11:08:09
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3a -flat -suppress -vhdl F:/2014050202010/miaobiao/top.vhf -w F:/2014050202010/miaobiao/top.sch
--Design Name: top
--Device: spartan3a
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity top is
   port ( carryin  : in    std_logic; 
          clk      : in    std_logic; 
          reset    : in    std_logic; 
          carryout : out   std_logic; 
          h1       : out   std_logic_vector (3 downto 0); 
          h10      : out   std_logic_vector (3 downto 0); 
          m1       : out   std_logic_vector (3 downto 0); 
          m10      : out   std_logic_vector (3 downto 0); 
          s1       : out   std_logic_vector (3 downto 0); 
          s10      : out   std_logic_vector (3 downto 0));
end top;

architecture BEHAVIORAL of top is
   signal XLXN_2   : std_logic;
   signal XLXN_9   : std_logic;
   signal XLXN_16  : std_logic;
   signal XLXN_22  : std_logic;
   signal XLXN_31  : std_logic;
   component counter6
      port ( clk      : in    std_logic; 
             carryin  : in    std_logic; 
             reset    : in    std_logic; 
             carryout : out   std_logic; 
             timeout  : out   std_logic_vector (3 downto 0));
   end component;
   
   component counter10
      port ( clk      : in    std_logic; 
             carryin  : in    std_logic; 
             reset    : in    std_logic; 
             carryout : out   std_logic; 
             timeout  : out   std_logic_vector (3 downto 0));
   end component;
   
begin
   XLXI_1 : counter6
      port map (carryin=>XLXN_2,
                clk=>clk,
                reset=>reset,
                carryout=>carryout,
                timeout(3 downto 0)=>h10(3 downto 0));
   
   XLXI_2 : counter10
      port map (carryin=>XLXN_31,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_2,
                timeout(3 downto 0)=>h1(3 downto 0));
   
   XLXI_3 : counter10
      port map (carryin=>XLXN_9,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_22,
                timeout(3 downto 0)=>s10(3 downto 0));
   
   XLXI_4 : counter10
      port map (carryin=>carryin,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_9,
                timeout(3 downto 0)=>s1(3 downto 0));
   
   XLXI_5 : counter10
      port map (carryin=>XLXN_22,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_16,
                timeout(3 downto 0)=>m1(3 downto 0));
   
   XLXI_6 : counter6
      port map (carryin=>XLXN_16,
                clk=>clk,
                reset=>reset,
                carryout=>XLXN_31,
                timeout(3 downto 0)=>m10(3 downto 0));
   
end BEHAVIORAL;


